Fujitsu FR family 32-bit microcontroller instruction manue Manual do Utilizador

FUJITSU SEMICONDUCTORCONTROLLER MANUALFR Family32-BIT MICROCONTROLLERINSTRUCTION MANUALCM71-00101-5E

vi CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU ... 535.1 Pipeline Operation ...

76CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.5 ADDN (Add Word Data of Source Register to Destination Register)Adds the word data in "Rj" an

77CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.6 ADDN (Add Immediate Data to Destination Register)Adds the result of the higher 28 bits of 4-bit immedi

78CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.7 ADDN2 (Add Immediate Data to Destination Register)Adds the result of the higher 28 bits of 4-bit immed

79CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.8 SUB (Subtract Word Data in Source Register from Destination Register)Subtracts the word data in "

80CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register)Subtracts the word

81CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.10 SUBN (Subtract Word Data in Source Register from Destination Register)Subtracts the word data in &quo

82CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.11 CMP (Compare Word Data in Source Register and Destination Register)Subtracts the word data in "R

83CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.12 CMP (Compare Immediate Data of Source Register and Destination Register)Subtracts the result of the h

84CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.13 CMP2 (Compare Immediate Data and Destination Register)Subtracts the result of the higher 28 bits of 4

85CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.14 AND (And Word Data of Source Register to Destination Register)Takes the logical AND of the word data

vii7.35 MULU (Multiply Unsigned Word Data) ... 1227.36 MULH

86CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.15 AND (And Word Data of Source Register to Data in Memory)Takes the logical AND of the word data at mem

87CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: AND R2, @R3R2 123456781234567C 1111 0000123 4 5678NZVCCCRR2R3R3CCR0000 1010 1010NZVC0000

88CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.16 ANDH (And Half-word Data of Source Register to Data in Memory)Takes the logical AND of the half-word

89CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: ANDH R2, @R3R2 123456781234567A 0000 11001234 5678NZVCCCRR2R3R3CCR0000 1010NZVC0000 1234

90CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.17 ANDB (And Byte Data of Source Register to Data in Memory)Takes the logical AND of the byte data at me

91CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: ANDB R2, @R3R2 1234567812345679 0000 00101234 5678NZVCCCRR2R3R3CCR0000 11NZVC0000 1234 5

92CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.18 OR (Or Word Data of Source Register to Destination Register)Takes the logical OR of the word data in

93CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.19 OR (Or Word Data of Source Register to Data in Memory)Takes the logical OR of the word data at memory

94CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: OR R2, @R3R2 123456781234567C 1111 00001234 5678NZVCCCRR2R3R3CCR0000 1010 1010NZVC0000

95CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.20 ORH (Or Half-word Data of Source Register to Data in Memory)Takes the logical OR of the half-word dat

viii 7.82 MOV (Move Word Data in Source Register to Destination Register) ... 1787.83 MOV (Move Word Data

96CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: ORH R2, @R3R2 123456781234567A 0000 11001234 5678NZVCCCRR2R3R3CCR0000 1010NZVC0000 1234

97CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.21 ORB (Or Byte Data of Source Register to Data in Memory)Takes the logical OR of the byte data at memor

98CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: ORB R2, @R3R2 1234567812345679 0000 00111234 5678NZVCCCRR2R3R3CCR0000 10NZVC0000 1234 56

99CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.22 EOR (Exclusive Or Word Data of Source Register to Destination Register)Takes the logical exclusive OR

100CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory)Takes the logical exclusive OR of t

101CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: EOR R2, @R3R2 123456781234567C 1111 00001234 5678NZVCCCRR2R3R3CCR0000 1010 1010NZVC0000

102CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory)Takes the logical exclusive O

103CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: EORH R2, @R3R2 123456781234567A 0000 11001234 5678NZVCCCRR2R3R3CCR0000 1010NZVC0000 123

104CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory)Takes the logical exclusive OR of

105CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: EORB R2, @R3R2 1234567812345679 0000 00111234 5678NZVCCCRR2R3R3CCR0000 10NZVC0000 1234

ix7.123 STILM (Set Immediate Data to Interrupt Level Mask Register) ... 2407.124 ADDSP (Add Stack

106CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.26 BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)Takes the logical AND of the

107CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: BANDL #0, @R312345678123456791234 5678NZVCCCRR3R3CCR0000 11NZVC00001234 5678Memory12345678123

108CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.27 BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)Takes the logical AND of the

109CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: BANDH #0, @R312345678123456791234 5678NZVCCCRR3R3CCR0000 11NZVC00001234 5678Memory12345678123

110CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.28 BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)Takes the logical OR of the 4-b

111CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: BORL #1, @R312345678123456791234 5678NZVCCCRR3R3CCR0000 00NZVC00001234 56781234567812345679

112CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.29 BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)Takes the logical OR of the 4-

113CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: BORH #1, @R312345678123456791234 5678NZVCCCRR3R3CCR0000 00NZVC00001234 56781234567812345679

114CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.30 BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)Takes the logical exclusive O

115CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: BEORL #1, @R312345678123456791234 5678NZVCCCRR3R3CCR0000 00NZVC00001234 5678Memory12345678123

x

116CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.31 BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)Takes the logical exclusive

117CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: BEORH #1, @R312345678123456791234 5678NZVCCCRR3R3CCR0000 00NZVC00001234 5678Memory12345678123

118CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.32 BTSTL (Test Lower 4 Bits of Byte Data in Memory)Takes the logical AND of the 4-bit immediate data an

119CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.33 BTSTH (Test Higher 4 Bits of Byte Data in Memory)Takes the logical AND of the 4-bit immediate data a

120CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.34 MUL (Multiply Word Data)Multiplies the word data in "Rj" by the word data in "Ri"

121CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: MUL R2, R3MDH MDL NZVCCCR CCR0000NZVC0010R2 R3 0000 00028000 0001MDH MDL R2 R3 0000

122CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.35 MULU (Multiply Unsigned Word Data)Multiplies the word data in "Rj" by the word data in &qu

123CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: MULU R2, R3MDH MDL NZVCCCR CCR0000NZVC0010R2 R3 0000 00028000 0001MDH MDL R2 R3 0000

124CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.36 MULH (Multiply Half-word Data)Multiplies the half-word data in the lower 16 bits of "Rj" b

125CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: MULH R2, R3MDH MDL NZVCCCR CCR0000NZVC1000R2 R3 FEDCBA980123 4567MDH MDL R2 R3 FEDCB

xiMain changes in this editionPage Changes (For details, refer to main body.)-Be sure to refer to the "Check Sheet" for the latest cautions

126CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.37 MULUH (Multiply Unsigned Half-word Data)Multiplies the half-word data in the lower 16 bits of "

127CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: MULUH R2, R3MDH MDL NZVCCCR CCR0000NZVC0000R2 R3 FEDCBA980123 4567MDH MDL R2 R3 FEDC

128CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.38 DIV0S (Initial Setting Up for Signed Division)This command is used for signed division in which the

129CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DIV0S R2Example: Actual use MDL ÷ R2 = MDL (quotient) ... MDH (remainder), signed calculationM

130CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.39 DIV0U (Initial Setting Up for Unsigned Division)This command is used for unsigned division in which

131CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DIV0U R2Example: Actual use MDL ÷ R2 = MDL (quotient) ... MDH (remainder), unsigned calculation

132CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.40 DIV1 (Main Process of Division)This instruction is used in unsigned division. It should be used in c

133CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DIV1 R2MDH MDL D1 D0 TSCR SCRD1 D0 T000000R200FF FFFFMDH MDL R20000 00010100 00000000 000000

134CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.41 DIV2 (Correction when Remainder is 0)This instruction is used in signed division. It should be used

135CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DIV2 R2MDH MDL D1 D0 TSCR SCRD1 D0 T000000R200FF FFFFMDH MDL R20000 000F0000 00000000 000F00

xii 38"4.3.1 User Interrupts" is changed.( "External" → "User" ), ( "external" → "user" )"

136CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.42 DIV3 (Correction when Remainder is 0)This instruction is used in signed division. It should be used

137CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.43 DIV4S (Correction Answer for Signed Division)This instruction is used in signed division. It should

138CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.44 LSL (Logical Shift to the Left Direction)Makes a logical left shift of the word data in "Ri&quo

139CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.45 LSL (Logical Shift to the Left Direction)Makes a logical left shift of the word data in "Ri&quo

140CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.46 LSL2 (Logical Shift to the Left Direction)Makes a logical left shift of the word data in "Ri&qu

141CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.47 LSR (Logical Shift to the Right Direction)Makes a logical right shift of the word data in "Ri&q

142CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.48 LSR (Logical Shift to the Right Direction)Makes a logical right shift of the word data in "Ri&q

143CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.49 LSR2 (Logical Shift to the Right Direction)Makes a logical right shift of the word data in "Ri&

144CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.50 ASR (Arithmetic Shift to the Right Direction)Makes an arithmetic right shift of the word data in &qu

145CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.51 ASR (Arithmetic Shift to the Right Direction)Makes an arithmetic right shift of the word data in &qu

xiii87"7.15 AND (And Word Data of Source Register to Data in Memory)" is changed.( "Instruction bit pattern : 1000 0100 0010 0011"

146CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.52 ASR2 (Arithmetic Shift to the Right Direction)Makes an arithmetic right shift of the word data in &q

147CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register)Loads 1 word of immediate data to "R

148CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register)Extends the 20-bit immediate data with 12

149CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register)Extends the 8-bit immediate data with 24 ze

150CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.56 LD (Load Word Data in Memory to Register)Loads the word data at memory address "Rj" to &qu

151CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.57 LD (Load Word Data in Memory to Register)Loads the word data at memory address "(R13 + Rj)"

152CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.58 LD (Load Word Data in Memory to Register)Loads the word data at memory address "(R14 + o8 × 4)&

153CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.59 LD (Load Word Data in Memory to Register)Loads the word data at memory address "(R15 + u4 × 4)&

154CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.60 LD (Load Word Data in Memory to Register)Loads the word data at memory address "R15" to &q

155CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.61 LD (Load Word Data in Memory to Register)Loads the word data at memory address "R15" to de

xiv 136"7.42 DIV3 (Correction when Remainder is 0)" is changed.( "Instruction bit pattern : 1001 1111 0110 0000" is added. )137&q

156CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: LD @ R15 +, MDH12345670123456741234 5674R15MDH 8765 43211234567012345674 8765 4321R151

157CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.62 LD (Load Word Data in Memory to Program Status Register)Loads the word data at memory address "

158CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: LD @ R15 +, PS12345670123456741234 5674FFFF F8D5PSR15 FFF8 F8C01234567012345674 FFF8 F

159CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.63 LDUH (Load Half-word Data in Memory to Register)Extends with zeros the half-word data at memory addr

160CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.64 LDUH (Load Half-word Data in Memory to Register)Extends with zeros the half-word data at memory addr

161CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.65 LDUH (Load Half-word Data in Memory to Register)Extends with zeros the half-word data at memory addr

162CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.66 LDUB (Load Byte Data in Memory to Register)Extends with zeros the byte data at memory address "

163CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.67 LDUB (Load Byte Data in Memory to Register)Extends with zeros the byte data at memory address "

164CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.68 LDUB (Load Byte Data in Memory to Register)Extends with zeros the byte data at memory address "

165CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.69 ST (Store Word Data in Register to Memory)Loads the word data in "Ri" to memory address &q

xv163"7.67 LDUB (Load Byte Data in Memory to Register)" is changed.( "Instruction bit pattern : 0000 0010 0010 0011" is added. )16

166CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.70 ST (Store Word Data in Register to Memory)Loads the word data in "Ri" to memory address &q

167CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.71 ST (Store Word Data in Register to Memory)Loads the word data in "Ri" to memory address &q

168CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.72 ST (Store Word Data in Register to Memory)Loads the word data in "Ri" to memory address &q

169CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.73 ST (Store Word Data in Register to Memory)Subtracts 4 from the value of "R15", stores the

170CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.74 ST (Store Word Data in Register to Memory)Subtracts 4 from the value of "R15", stores the

171CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.75 ST (Store Word Data in Program Status Register to Memory)Subtracts 4 from the value of "R15&quo

172CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.76 STH (Store Half-word Data in Register to Memory)Stores the half-word data in "Ri" to memor

173CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.77 STH (Store Half-word Data in Register to Memory)Stores the half-word data in "Ri" to memor

174CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.78 STH (Store Half-word Data in Register to Memory)Stores the half-word data in "Ri" to memor

175CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.79 STB (Store Byte Data in Register to Memory)Stores the byte data in "Ri" to memory address

xvi 185"7.88 CALL (Call Subroutine)" is changed.( "extension for use as the branch destination address" → "extension"

176CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.80 STB (Store Byte Data in Register to Memory)Stores the byte data in "Ri" to memory address

177CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.81 STB (Store Byte Data in Register to Memory)Stores the byte data in "Ri" to memory address

178CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.82 MOV (Move Word Data in Source Register to Destination Register)Moves the word data in "Rj"

179CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.83 MOV (Move Word Data in Source Register to Destination Register)Moves the word data in dedicated regi

180CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.84 MOV (Move Word Data in Program Status Register to Destination Register)Moves the word data in the pr

181CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.85 MOV (Move Word Data in Source Register to Destination Register)Moves the word data in general-purpos

182CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.86 MOV (Move Word Data in Source Register to Program Status Register)Moves the word data in general-pur

183CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: MOV R3, PSR3R3FFF3 F8D5 FFF3 F8D5FFF3 F8D5PS PSxxxx xxxxBefore execution After executionInstruct

184CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.87 JMP (Jump)This is a branching instruction with no delay slot.Branches to the address indicated by &q

185CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.88 CALL (Call Subroutine)This is a branching instruction with no delay slot.After storing the address o

xvii198"7.96 CALL:D (Call Subroutine)" is changed.( "CALL : D 120H LDI : 8 #0, R2 ; Instruction placed in delay slot" → &quo

186CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.89 CALL (Call Subroutine)This is a branching instruction with no delay slot.After storing the address o

187CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.90 RET (Return from Subroutine)This is a branching instruction with no delay slot.Branches to the addre

188CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.91 INT (Software Interrupt)Stores the values of the program counter (PC) and program status (PS) to the

189CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: INT #20H6809 6800 6809 68008088 8088FFFF F8F0R15 000FFF7Cxxxx xxxx 7FFFFFF87FFFFFFC80000000

190CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.92 INTE (Software Interrupt for Emulator)This software interrupt instruction is used for debugging. It

191CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: INTE6809 6800 6809 68008088 8088FFFF F8F0R15 000FFFD8xxxx xxxx 7FFFFFF87FFFFFFC80000000000F

192CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.93 RETI (Return from Interrupt)Loads data from the stack indicated by "R15" to the program co

193CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: RETI8088 8088FFF3 F8F18088 8088FFF3 F8F1R15 xxxx xxxx7FFFFFF87FFFFFFC800000007FFFFFF87FFFFFFC8

194CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.94 Bcc (Branch Relative if Condition Satisfied)This branching instruction has no delay slot.If the cond

195CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExecution cycles: Branch: 2 cyclesNot branch: 1 cycleInstruction format: Example: BHI label...label

xviii 238"7.121 ANDCCR (And Condition Code Register and Immediate Data)" is changed.( "Instruction bit pattern : 1000 0011 1111 1110&q

196CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.95 JMP:D (Jump)This branching instruction has a delay slot.Branches to the address indicated by "R

197CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.96 CALL:D (Call Subroutine)This is a branching instruction with a delay slot.After saving the address o

198CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: CALL:D labelLDI : 8 #0, R2 ; Instruction placed in delay slot...label: ; CALL: D instructio

199CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.97 CALL:D (Call Subroutine)This is a branching instruction with a delay slot.After saving the address o

200CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: CALL : D @R1LDI : 8 #1, R1 ; Instruction placed in delay slotThe instruction placed in the de

201CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.98 RET:D (Return from Subroutine)This is a branching instruction with a delay slot.Branches to the addr

202CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: RET : D MOV R0, R1 ; Instruction placed in delay slotThe instruction placed in the delay slot

203CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.99 Bcc:D (Branch Relative if Condition Satisfied)This is a branching instruction with a delay slot.If t

204CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExecution cycles: 1 cycleInstruction format: Example: BHI:D labelLDI :8 #255, R1 ; Instruction plac

205CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.100 DMOV (Move Word Data from Direct Address to Register)Transfers, to "R13", the word data a

xix263"A.1 Symbols Used in Instruction Lists" is chenged.● Symbols in Mnemonic and Operation Columns is changed.i8 ...( "128

206CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.101 DMOV (Move Word Data from Register to Direct Address)Transfers the word data in "R13" to

207CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.102 DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address)Transfers the

208CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOV @88H, @R13+1414 2135 1414 21351414 2135R13 Memory00000088 FFFF1248FFFF124CFFFF1248FFF

209CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.103 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)Transfers the

210CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOV @R13+, @54H8947 91AF8947 91AF8947 91AFR13 00000054 FFFF1248FFFF124CFFFF1248FFFF124C000

211CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.104 DMOV (Move Word Data from Direct Address to Pre-decrement Register Indirect Address)Decrements the

212CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOV @2CH, @ – R1582A2 82A9 82A2 82A982A2 82A9R15 Memory0000002C 7FFFFF847FFFFF880000002C7F

213CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.105 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)Transfers the

214CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOV @R15+, @38H8343 834A8343 834A8343 834AR15 Memory00000038 7FFEEE807FFEEE84000000387FFE E

215CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.106 DMOVH (Move Half-word Data from Direct Address to Register)Transfers the half-word data at the dire

xx 267"Table A.2-6 Shift Instructions (9 Instructions)" is changed.( "Ri <<(u4+16) → Ri" → "Ri <<{u4+16} →

216CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.107 DMOVH (Move Half-word Data from Register to Direct Address)Transfers the half-word data from "

217CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.108 DMOVH (Move Half-word Data from Direct Address to Post Increment Register Indirect Address)Transfer

218CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOVH @88H, @R13+ 1374R13 00000088 FF000052FF000054FF00 0052R13FF00 0054Instruction bit patt

219CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.109 DMOVH (Move Half-word Data from Post Increment Register Indirect Address to Direct Address)Transfer

220CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOVH @R13+, @52H 8933R13 00000052 FF801220FF801222FF801220FF801222FF80 1220R13FF80 1222Inst

221CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.110 DMOVB (Move Byte Data from Direct Address to Register)Transfers the byte data at the address indica

222CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.111 DMOVB (Move Byte Data from Register to Direct Address)Transfers the byte data from "R13"

223CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.112 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address)Moves the byt

224CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOVB @71H, @R13+ 99R13 Memory00000071xxxx xx 88001234880012358800 1234R138800 1235Instructio

225CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.113 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address)Transfers the

1CHAPTER 1FR FAMILY OVERVIEWThis chapter describes the features of the FR FAMILY CPU core, and provides sample configurations.1.1 Features of the FR

226CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOVB @R13+, @57H 55 5555R13 Memory00000057xxxx xx FF801220FF801221FF80 1220R13FF80 1221Instr

227CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.114 LDRES (Load Word Data in Memory to Resource)Transfers the word data at the address indicated by &qu

228CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.115 STRES (Store Word Data in Resource to Memory)Transfers the word data at the resource on channel &qu

229CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.116 COPOP (Coprocessor Operation)Transfers the 16-bit data consisting of parameters "CC", &qu

230CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: COPOP #15, #1, CR3, CR416-bit data is transferred through the bus to the coprocessor indicated b

231CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.117 COPLD (Load 32-bit Data from Register to Coprocessor Register)Transfers the 16-bit data consisting

232CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: COPLD #15, #4, R8, CR116-bit data is transferred through the bus to the coprocessor indicated by

233CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.118 COPST (Store 32-bit Data from Coprocessor Register to Register)Transfers the 16-bit data consisting

234CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: COPST #15, #4, CR2, R416-bit data is transferred through the bus to the coprocessor indicated by

235CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.119 COPSV (Save 32-bit Data from Coprocessor Register to Register)Transfers the 16-bit data consisting

2CHAPTER 1 FR FAMILY OVERVIEW1.1 Features of the FR Family CPU CoreThe FR family CPU core features proprietary Fujitsu architecture and is designed f

236CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: COPSV #15, #4, CR2, R416-bit data is transferred through the bus to the coprocessor indicated by

237CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.120 NOP (No Operation)This instruction performs no operation. NOP (No Operation)Assembler format: NOPO

238CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.121 ANDCCR (And Condition Code Register and Immediate Data)Takes the logical AND of the byte data in th

239CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.122 ORCCR (Or Condition Code Register and Immediate Data)Takes the logical OR of the byte data in the c

240CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.123 STILM (Set Immediate Data to Interrupt Level Mask Register)Transfers the immediate data to the inte

241CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.124 ADDSP (Add Stack Pointer and Immediate Data)Adds 4 times the immediate data as a signed extended va

242CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.125 EXTSB (Sign Extend from Byte Data to Word Data)Extends the byte data indicated by "Ri" to

243CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.126 EXTUB (Unsign Extend from Byte Data to Word Data)Extends the byte data indicated by "Ri"

244CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.127 EXTSH (Sign Extend from Byte Data to Word Data)Extends the half-word data indicated by "Ri&quo

245CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.128 EXTUH (Unsigned Extend from Byte Data to Word Data)Extends the half-word data indicated by "Ri

3CHAPTER 1 FR FAMILY OVERVIEW1.2 Sample Configuration of an FR Family DeviceFR family devices have block configuration with bus connections between i

246CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.129 LDM0 (Load Multiple Registers)The "LDM0" instruction accepts registers in the range R0 to

247CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: LDM0 (R3, R4) 90BC93638343 834A xxxx xxxx7FFFFFC07FFFFFC47FFFFFC8R157FFF FFC0R4R3Instruction

248CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.130 LDM1 (Load Multiple Registers)The LDM1 instruction accepts registers in the range R8 to R15 as memb

249CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: LDM1 (R10, R11, R12) Table 7.130-1 Bit Values and Register Numbers for "reglist" (LD

250CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.131 STM0 (Store Multiple Registers)The "STM0" instruction accepts registers in the range R0 t

251CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: STM0 (R2, R3) 90BC93638343 834A xxxx xxxx7FFFFFC07FFFFFC47FFFFFC8R157FFF FFC8R3R2Instruction b

252CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.132 STM1 (Store Multiple Registers)The "STM1" instruction accepts registers in the range R8 t

253CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: STM1 (R10, R11, R12) 90BC93638DF7 88E4 xxxx xxxx7FFFFFC47FFFFFC87FFFFFCCR157FFF FFCCR12R10Inst

254CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.133 ENTER (Enter Function)This instruction is used for stack frame generation processing for high level

255CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: ENTER #0CH 7FFF FFF8 7FFFFFF87FFFFFFC80000000R14Instruction bit pattern : 0000 1111 0000 0011

4CHAPTER 1 FR FAMILY OVERVIEW1.3 Sample Configuration of the FR Family CPUThe FR family CPU core features a block configuration organized around gene

256CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.134 LEAVE (Leave Function)This instruction is used for stack frame release processing for high level la

257CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: LEAVE7FFF FFEC 7FFFFFF87FFFFFFC80000000R14 7FFF FFF47FFFFFF47FFFFFF07FFFFFEC8000 00008000 00

258CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.135 XCHB (Exchange Byte Data)Exchanges the contents of the byte address indicated by "Rj" and

259CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: XCHB @R1, R0R1 800000018000000280000003800000018000000280000003xxxxxxxxFDR1 788000 00028000

260CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS

261APPENDIXThe appendix section includes lists of CPU instructions used in the FR family, as well as instruction map diagrams.APPENDIX A Instruction

262APPENDIX A Instruction ListsAPPENDIX A Instruction ListsAppendix A includes a description of symbols used in instruction lists, plus the instructi

263APPENDIX A Instruction ListsA.1 Symbols Used in Instruction ListsThis section describes symbols used in the FR family instruction lists. Symbols

264APPENDIX A Instruction Lists● Format ColumnA to F ... format TYPE-A through F as described in Section "6.1 Instruction Formats"

265APPENDIX A Instruction ListsA.2 Instruction ListsThe full instruction set of the FR family CPU is 165 instructions, consisting of the following s

5CHAPTER 2MEMORY ARCHITECTUREThis chapter describes memory space in the FR family CPU.Memory architecture includes the allocation of memory space as w

266APPENDIX A Instruction ListsTable A.2-2 Compare Instructions (3 Instructions) Mnemonic Format OP CYCFLAGNZVCOperation RemarksCMP Rj, RiCMP

267APPENDIX A Instruction ListsTable A.2-5 Multiply/Divide Instructions (10 Instructions) Mnemonic Format OP CYCFLAGNZVCOperation RemarksMUL R

268APPENDIX A Instruction ListsNote:The field "o8" in the TYPE-B instruction format and the field "u4" in the TYPE-C format have

269APPENDIX A Instruction ListsNote:The field "o8" in the TYPE-B instruction format and the field "u4" in the TYPE-C format have

270APPENDIX A Instruction ListsNotes:• The field "rel8" in the TYPE-D instruction format and the field "rel11" in the TYPE-F form

271APPENDIX A Instruction ListsNotes:• The field "rel8" in the TYPE-D instruction format and the field "rel11" in the TYPE-F form

272APPENDIX A Instruction ListsNote:The field "dir" in the TYPE-D instruction format has the following relation to the values "dir8&qu

273APPENDIX A Instruction ListsNotes:• In the "ADD SP" instruction, the field "s8" in the TYPE-D instruction format has the follo

274APPENDIX B Instruction MapsAPPENDIX B Instruction MapsThis appendix presents FR family instruction map and "E" format.B.1 Instruction M

275APPENDIX B Instruction MapsB.1 Instruction MapThis section shows instruction maps for FR family CPU. Instruction MapTable B.1-1 Instruction MapH

FUJITSU LIMITEDFR Family32-BIT MICROCONTROLLERINSTRUCTION MANUAL

6CHAPTER 2 MEMORY ARCHITECTURE2.1 FR Family Memory SpaceThe FR family controls memory space in byte units, and provides linear designation of 32-bit

276APPENDIX B Instruction MapsB.2 "E" FormatThis section shows "E" format for FR family CPU. "E" Format-: UndefinedTab

277INDEXINDEXThe index follows on the next page.This is listed in alphabetical order.

278INDEXIndexAADDADD (Add 4-bit Immediate Data to Destination Register)...73ADD (Add Word Data of Source R

279INDEXBit PatternsRelation between Bit Patterns "Ri" and "Rj" and Register Values... 64BORHBOR

280INDEXExamples of Programing Delayed Branching Instructions...62Overview of Branching with Delayed Branching

281INDEXDMOVB (Move Byte Data from Register to Direct Address)... 222DMOVHDMOVH (Move Half-word Data from Di

282INDEXInterlocking Produced by Reference to "R15" and General-purpose Registers after Changing the "S" Flag ...

283INDEXPrecautionary Information for Use of "INT" Instructions... 45Time to Start of Trap Processin

284INDEXLDI:8 (Load Immediate 8-bit Data to Destination Register)...149Load Multiple RegistersLDM0 (Load Mul

285INDEXNNMIRelation of Step Trace Traps to "NMI" and External Interrupts... 47No OperationNOP (N

7CHAPTER 2 MEMORY ARCHITECTURE2.1.1 Direct Address AreaThe lower portion of the address space is used for the direct address area. Instructions that

286INDEXInterrupt Level Mask Register (ILM: Bit 20 to bit 16)...19LD (Load Word Data in Memor

287INDEXEORB (Exclusive Or Byte Data of Source Register to Data in Memory)... 104EORH (Exclusive Or Half-word Data of So

288INDEXSystem Stack PointerFunctions of the System Stack Pointer and User Stack Pointer ...28System Sta

CM71-00101-5EFUJITSU SEMICONDUCTOR • CONTROLLER MANUALFR Family32-BIT MICROCONTROLLERINSTRUCTION MANUALDecember 2007 the fifth editionPublished FUJITS

8CHAPTER 2 MEMORY ARCHITECTURE2.1.2 Vector Table AreaAn area of 1 Kbyte beginning with the address shown in the table base register (TBR) is used to

9CHAPTER 2 MEMORY ARCHITECTURE Contents of Vector Table AreasA vector table is composed of entry addresses for each of the "EIT" processin

10CHAPTER 2 MEMORY ARCHITECTURE2.2 Bit Order and Byte OrderThis section describes the order in which three types of data, 8, 16, and 32 bits, are pla

11CHAPTER 2 MEMORY ARCHITECTURE2.3 Word AlignmentIn the FR family, the type of data length used determines restrictions on thedesignation of memory a

12CHAPTER 2 MEMORY ARCHITECTURE

13CHAPTER 3REGISTER DESCRIPTIONSThis chapter describes the registers used in the FR family CPU.3.1 FR Family Register Configuration3.2 General-purpo

14CHAPTER 3 REGISTER DESCRIPTIONS3.1 FR Family Register ConfigurationFR family devices use two types of registers, general-purpose registers and dedi

15CHAPTER 3 REGISTER DESCRIPTIONS3.2 General-purpose RegistersThe FR family CPU uses general-purpose registers to hold the results of various calcula

16CHAPTER 3 REGISTER DESCRIPTIONS● R14 (Frame Pointer: FP)• Index register for load/store to memory instructions[Example: LD @(R14, disp10), Ri]• Fra

17CHAPTER 3 REGISTER DESCRIPTIONS3.3 Dedicated RegistersThe FR family has six 32-bit registers reserved for various special purposes, plus one 64-bit

18CHAPTER 3 REGISTER DESCRIPTIONS3.3.1 Program Counter (PC)This register indicates the address containing the instruction that is currently executing

19CHAPTER 3 REGISTER DESCRIPTIONS3.3.2 Program Status (PS) The program status (PS) indicates the status of program execution, and consists of the fol

20CHAPTER 3 REGISTER DESCRIPTIONSFigure 3.3-4 "ILM" Register Functions● Range of ILM Program Setting ValuesIf the original value of the re

21CHAPTER 3 REGISTER DESCRIPTIONS Condition Code Register (CCR: Bit 07 to bit 00)● Bit Configuration of the "CCR" Figure 3.3-6 Bit Config

22CHAPTER 3 REGISTER DESCRIPTIONS Note on PS RegisterBecause of prior processing of the PS register by some commands, a break may be brought in an i

23CHAPTER 3 REGISTER DESCRIPTIONS3.3.3 Table Base Register (TBR)The Table Base Register (TBR) designates the table containing the entry address for &

24CHAPTER 3 REGISTER DESCRIPTIONS Table Base Register ConfigurationFigure 3.3-8 shows the bit configuration of the table base register. Figure 3.3-

25CHAPTER 3 REGISTER DESCRIPTIONS3.3.4 Return Pointer (RP)The return pointer (RP) is a register used to contain the program counter (PC) value during

iPREFACE Objectives and intended readerThe FR* family CPU core features proprietary Fujitsu architecture and is designed for controllerapplications u

26CHAPTER 3 REGISTER DESCRIPTIONS Return Pointer ConfigurationFigure 3.3-11 shows the bit configuration of the return pointer. Figure 3.3-11 Retur

27CHAPTER 3 REGISTER DESCRIPTIONS3.3.5 System Stack Pointer (SSP), User Stack Pointer (USP)The system stack pointer (SSP) and user stack pointer (USP

28CHAPTER 3 REGISTER DESCRIPTIONSFigure 3.3-13 Example of Stack Pointer Operation in Execution of Instruction "ST R13, @-R15" when "S

29CHAPTER 3 REGISTER DESCRIPTIONS3.3.6 Multiplication/Division Register (MD)The multiplication/division register (MD) is a 64-bit register used to co

30CHAPTER 3 REGISTER DESCRIPTIONS Configuration of the "MD" RegisterFigure 3.3-17 shows the bit configuration of the "MD". Figu

31CHAPTER 4RESET AND "EIT"PROCESSINGThis chapter describes reset and "EIT" processing in the FR family CPU. A reset is a means of

32CHAPTER 4 RESET AND "EIT" PROCESSING4.1 Reset Processing4.2 Basic Operations in "EIT" Processing4.3 Interrupts4.4 Exception

33CHAPTER 4 RESET AND "EIT" PROCESSING4.1 Reset ProcessingA reset is a means of forcibly terminating the currently executing process, initi

34CHAPTER 4 RESET AND "EIT" PROCESSING4.2 Basic Operations in "EIT" ProcessingInterrupts, exceptions and traps are similar operat

35CHAPTER 4 RESET AND "EIT" PROCESSING Vector Table ConfigurationVector tables are located in the main memory, occupying an area of 1 Kbyt

ii Organization of this manualThis manual consists of the following 7 chapters and 1 appendix:CHAPTER 1 FR FAMILY OVERVIEWThis chapter describes t

36CHAPTER 4 RESET AND "EIT" PROCESSING Saved RegistersExcept in the case of reset processing, the values of the "PS" and "P

37CHAPTER 4 RESET AND "EIT" PROCESSING4.3 InterruptsInterrupts originate independently of the instruction sequence. They are processed by s

38CHAPTER 4 RESET AND "EIT" PROCESSING4.3.1 User InterruptsUser interrupts originate as requests from peripheral circuits. Each interrupt r

39CHAPTER 4 RESET AND "EIT" PROCESSING Time to Start of Interrupt ProcessingThe time required to start interrupt processing can be express

40CHAPTER 4 RESET AND "EIT" PROCESSING4.3.2 Non-maskable Interrupts (NMI)Non-maskable interrupts (NMI) are interrupts that cannot be masked

41CHAPTER 4 RESET AND "EIT" PROCESSING "PC" Values Saved for Non-maskable InterruptsWhen an "NMI" is accepted by the p

42CHAPTER 4 RESET AND "EIT" PROCESSING4.4 Exception ProcessingExceptions originate from within the instruction sequence. Exceptions are pro

43CHAPTER 4 RESET AND "EIT" PROCESSING4.4.1 Undefined Instruction ExceptionsUndefined instruction exceptions are caused by attempts to exec

44CHAPTER 4 RESET AND "EIT" PROCESSING4.5 TrapsTraps originate from within the instruction sequence. Traps are processed by first saving th

45CHAPTER 4 RESET AND "EIT" PROCESSING4.5.1 "INT" InstructionsThe "INT" instruction is used to create a software trap.T

iiiCopyright ©1997-2007 FUJITSU LIMITED All rights reserved.• The contents of this document are subject to change without notice. Customers are advise

46CHAPTER 4 RESET AND "EIT" PROCESSING4.5.2 "INTE" InstructionThe "INTE" instruction is used to create a software trap

47CHAPTER 4 RESET AND "EIT" PROCESSING4.5.3 Step Trace TrapsStep trace traps are traps used by debuggers. This type of trap can be created

48CHAPTER 4 RESET AND "EIT" PROCESSING4.5.4 Coprocessor Not Found TrapsCoprocessor not found traps are generated by executing coprocessor i

49CHAPTER 4 RESET AND "EIT" PROCESSING4.5.5 Coprocessor Error TrapA coprocessor error trap is generated when an error has occurred in a cop

50CHAPTER 4 RESET AND "EIT" PROCESSING Saving and Restoring Coprocessor Error InformationWhen a coprocessor is used in a multi-tasking env

51CHAPTER 4 RESET AND "EIT" PROCESSING4.6 Priority LevelsWhen multiple "EIT" requests occur at the same time, priority levels are

52CHAPTER 4 RESET AND "EIT" PROCESSING Priority of Multiple ProcessesWhen the acceptance of an "EIT" source results in the maski

53CHAPTER 5PRECAUTIONARYINFORMATION FOR THE FRFAMILY CPUThis chapter presents precautionary information related to the use of the FR family CPU.5.1 P

54CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU5.1 Pipeline OperationThe FR family CPU processes all instructions using a 5-stage pipelin

55CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU5.2 Pipeline Operation and Interrupt ProcessingThe FR family CPU processes all instruction

iv

56CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU5.3 Register HazardsThe FR family CPU executes program steps in the order in which they ar

57CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU InterlockingInstructions which are relatively slow in loading data to the CPU may cause

58CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU5.4 Delayed Branching ProcessingBecause the FR family CPU features pipeline operation, bra

59CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU•AND Rj, @Ri ANDH Rj, @RiANDB Rj, @RiOR Rj, @RiORH Rj, @RiORB Rj, @RiEOR Rj, @RiEORH Rj, @

60CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU5.4.1 Processing Non-delayed Branching InstructionsThe FR family CPU processes non-delayed

61CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU5.4.2 Processing Delayed Branching InstructionsThe FR family CPU processes delayed branchi

62CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU Examples of Programing Delayed Branching InstructionsAn example of programing a delayed

63CHAPTER 6INSTRUCTION OVERVIEWThis chapter presents an overview of the instructions used with the FR family CPU.All FR family CPU instructions are in

64CHAPTER 6 INSTRUCTION OVERVIEW6.1 Instruction FormatsThe FR family CPU uses six types of instruction format, TYPE-A through TYPE-F. Instruction Fo

65CHAPTER 6 INSTRUCTION OVERVIEW Relation between Bit Pattern "Rs" and Register ValuesTable 6.1-2 shows the relation between dedicated reg

vCONTENTSCHAPTER 1 FR FAMILY OVERVIEW ... 11.1 Features of the FR Family C

66CHAPTER 6 INSTRUCTION OVERVIEW6.2 Instruction Notation FormatsFR family CPU instructions are written in the following three notation formats.• Calc

67CHAPTER 7DETAILED EXECUTIONINSTRUCTIONSThis chapter presents each of the execution instructions used by the FR family assembler, in reference format

68CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)7.5 ADDN (Add Word Data o

69CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.40 DIV1 (Main Process of Division)7.41 DIV2 (Correction when Remainder is 0)7.42 DIV3 (Correction when R

70CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.77 STH (Store Half-word Data in Register to Memory)7.78 STH (Store Half-word Data in Register to Memory)

71CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.110 DMOVB (Move Byte Data from Direct Address to Register)7.111 DMOVB (Move Byte Data from Register to D

72CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.1 ADD (Add Word Data of Source Register to Destination Register)Adds word data in "Rj" to word

73CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.2 ADD (Add 4-bit Immediate Data to Destination Register)Adds the result of the higher 28 bits of 4-bit i

74CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.3 ADD2 (Add 4-bit Immediate Data to Destination Register)Adds the result of the higher 28 bits of 4-bit

75CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)Adds the word data in &qu